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? 2004 microchip technology inc. preliminary ds21894a-page 1 mcp2122 features ? pinout compatible with hsdl-7000 ? compliant with irda ? standard physical layer specification (version 1.3) ? uart to irda standard encoder/decoder - interfaces with irda standard compliant transceiver ? baud rates: - up to irda standard 115.2 kbaud operation ? transmit/receive formats (bit width) supported: -1.63s ? low-power mode (2 a at 1.8v, +125c) cmos technology ? low-voltage operation ? extended temperature range ? low power consumption package types block diagram irda family selection pdip, soic mcp2122 v ss 16xclk reset rxir txir v dd tx rx 1 2 3 4 8 7 6 5 encode decode tx txir rx rxir reset mcp2122 reset baud rate generator logic 16xclk device baud rate encoder/ decoder protocol layer handler clock source host uart baud rate selection comment host uart ir mcp2120 2400 - 312,500 (1) 2400 - 312,500 (1) yes no xtal hw/sw mcp2122 2400 - 115,200 (1) 2400 - 312,500 (1) yes no 16xclk by 16xclk extended temperature range (-40c to +125c) mcp2140 9600 9600 yes ircomm (3) xtal none -fixed mcp2150 9600 - 115,200 (2) 9600 - 115,200 (2) yes ircomm (3) xtal hw host uart easily interfaces to a pc?s serial port (dte) mcp2155 9600 - 115,200 (2) 9600 - 115,200 (2) yes ircomm (3) xtal hw host uart easily interfaces to a modem?s serial port (dce) note 1: the host uart and the ir operate at the same baud rates. 2: the host uart baud rate and the ir baud rates operate independent of each other. 3: supports the 9-wire ?cooked? service class of the ircomm application layer protocol. infrared encoder/decoder
mcp2122 ds21894a-page 2 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds21894a-page 3 mcp2122 1.0 device overview the mcp2122 is a stand-alone irda standard encoder/ decoder device that is pinout-compatible with the agilent ? hsdl-7000 encoder/decoder. the mcp2122 has two interfaces: the host uart interface and the ir interface (see figure 1-1). the host uart interfaces to the uart of the host controller. the host controller is the device in the embedded system that transmits and receives the data. the ir interface connects to an infrared (ir) optical transceiver circuit, which converts electrical pulses into ir light (encode) and converts ir light into electrical pulses (decode). this ir optical transceiver circuit could be either a stan- dard infrared (ir) optical transceiver (such as a vishay ? tfdu 4100) or it could be implemented with discrete components. for additional information, please refer to application note 243, ?fundamentals of the infrared physical layer? (ds00243). when the host controller transmits the uart format data, the mcp2122 receives this uart data and encodes (modulates) the data bit by bit. this encoded data is then output as electrical pulses to the ir trans- ceiver. the ir transceiver will then convert these electrical pulses to ir light pulses. the ir transceiver also receives ir light pulses (data), which are outputted as electrical pulses. the mcp2122 decodes (demodulates) thes e electrical pulses, with the data then transmitted by the mcp2122 uart. this modulation and demodulation method is performed in accordance with the irda standard. table 1-1 shows an overview of some of the device features. figure 1-1 shows a typical application block diagram. table 1-2 shows the pin definitions of the mcp2122 in normal operation. table 1-1: mcp2122 features overview infrared technology features: ? universal standard for connecting portable computing devices ? easy, effortless implementation ? economical alternative to other connectivity solutions ? reliable, high speed connection ? safe to use in any environ ment; can even be used during air travel ? eliminates the hassle of cables ? allows pc?s and non-pc?s to communicate to each other ? enhances mobility by allowing users to easily connect 1.1 applications some applications where an ir interface ( mcp2122 ) could be used include: ? data logging/data exchange ? system setup ? system diagnostic read out ? manufacturing configuration ? host controller firmware updates ? system control figure 1-1: system bl ock diagram features mcp2122 serial communications: uart, ir baud rate selection: 16xclk low power mode: yes resets: (and delays) reset pin (none) packages: 8-pin pdip 8-pin soic encode decode tx txir rx rxir reset mcp2122 picmicro ? so si tfdu 4100 uart txd rxd reset logic clock logic 16xclk clock host uart interface ir interface host controller protocol handler optical transceiver (i/o) mcu
mcp2122 ds21894a-page 4 preliminary ? 2004 microchip technology inc. table 1-2: pin description pin name pin number pin type buffer type pdip soic description 16xclk 1 1 i st 16x external clock source input tx 2 2 i st asynchronous receiv e from host controller uart rx 3 3 o ? asynchronous transm it to host controller uart v ss 4 4 ? p ground reference for logic and i/o pins reset 5 5 i st resets the device h = normal operation l = device in reset rxir 6 6 i st asynchronous receive from infrared transceiver txir 7 7 o ? asynchronous transmit to infrared transceiver v dd 8 8 ? p positive supply for logic and i/o pins legend: st = schmitt trigger i nput with cmos levels i = input o = output p = power
? 2004 microchip technology inc. preliminary ds21894a-page 5 mcp2122 2.0 device operation the mcp2122 is a low-cost infrared encoder/decoder. the baud rate is the same for the host uart and ir interfaces and is determined by the frequency of the 16xclk signal, with a maximum baud rate of 115.2 kbaud. the mcp2122 is made up of these functional modules: ? clock driver (16xclk) ? reset ? ir encoder/decoder - irda standard encoder - irda standard decoder the 16xclk circuit allows a clock input to provide the device clock. the reset circuit supports an external reset signal. the ir encoder logic takes a data bit and converts it to the irda signal according to the irda standard physical layer specification, while the ir decoder logic takes the irda standard signal and converts it to 8-bit data bytes. 2.1 power-up as the device is powered up, there will be a voltage range where the device will not operate properly. the device should be reset once the device has entered the normal operating range (from an out-of-voltage condition). the reset pin ma y then be forced high. other device operating parame ters (such as frequency, temperature, etc.) must also be within their operating ranges when the device ex its reset. otherwise, the device may not function as desired. 2.2 device reset the mcp2122 is forced in to the known state (reset) when the reset pin is in the low state. once the reset pin is brought to a high state, the device begins normal operation (if the device operating parameters are met). table 2-1 shows the states of the output pins while the device is in re set (reset = low). table 2-2 shows the state of the output pins once the device exits reset, reset = l h (device in normal operation mode). the mcp2122 has a reset noise filter in the reset input signal path. the filter will detect and ignore small pulses. using the reset pin to en ter a low-power state is discussed in section 2.9 ?minimizing power? . table 2-1: default output pin states in device reset table 2-2: default output pin states after device reset (reset = l h) 2.3 decoupling it is highly recommended that the mcp2122 have a decoupling capacitor (c byp ). a 0.01 f capacitor is recommended as a starting value, but evaluation of the best value for your circuit/layout should be done. place this decoupling capacitor (c byp ) as close to the mcp2122 as possible ( see figure 2-1). figure 2-1: device decoupling input pin output pin state comments name state rx txir reset l h l device in reset mode input pin output pin state comments name state rx txir tx l ? l h l after 7 - 8 16xclk pulses, the txir pin will pulse high. h?l rxir l h l ? after 4 16xclk pulses, rx = l. hh? v dd (bypass capacitor) mcp2122 v dd reset v ss 16xclk tx rx txir rxir c byp
mcp2122 ds21894a-page 6 preliminary ? 2004 microchip technology inc. 2.3.1 brown-outs some applications may subject the mcp2122 to a brown-out condition. good design practice requires that when a system is in brown-out, the system should be in reset to ensure that the system is in a known state when the system ex its the brown-out. this brown-out circuitry is external to the mcp2122. 2.3.1.1 external brown-out reset circuits figure 2-2 shows a circuit for external brown-out protection using the tcm809 device. figure 2-3 and figure 2-4 illustrate two examples of external circuitry that may be implemented. each option needs to be evaluated to determine if they satisfy the requirements of the application. figure 2-2: external brown-out protection using the tcm809 figure 2-3: external brown-out protection circuit 1 figure 2-4: external brown-out protection circuit 2 v ss rst tcm809 v dd mcp2122 v dd reset note 1: resistors should be adjusted for the characteristics of the transistor. 2: this circuit will activate reset when v dd goes below (vz + 0.7v), where vz = zener voltage. v dd 33 k ? 10 k ? 40 k ? v dd reset mcp2122 q1 r2 40 k ? v dd reset mcp2122 r1 q1 v dd note 1: this circuit is less expensive, but less accurate. tran sistor q1 turns off when v dd is below a certain level such that: 2: resistors should be adjusted for the characteristics of the transistor. v dd ? r1 r1 + r2 = 0.7v
? 2004 microchip technology inc. preliminary ds21894a-page 7 mcp2122 2.4 16xclk (bit clock) the mcp2122 requires an external clock source to operate. the 16xclk pin is the device clock input (see figure 2-5) and is independent of the host uart interface or the ir interf ace. the 16xclk determines all timing during device operation. it is the edge of the 16xclk pin that causes activity to occur. the 16xclk signal can also be referred to as a bit clock (bitclk). there are 16 bitclks for each bit time. the bitclks are used for the generation of the start bit, the eight data bits and the stop bit. when the embedded system could be receiving ir communication, the mcp2122 is required to have the 16xclk signal clocking at the expected frequency and have minimal variation in frequency. between data bytes (stop bit to start bit), the 16xclk frequency can be changed. this may occur in systems where the host controller is implementin g one of the irda standard application layer protoc ols (such as irobex). when the embedded system does not want to receive ir communications, the 16xclk clock can be disabled (static). this will reduce the power consumption of the system. figure 2-6 shows the relationship of the 16xclk signal to the rxir input, which then determines the rx output signal. figure 2-7 shows the relationship of the 16xclk signal to the tx input, which then determines the txir output signal. for device timing information, refer to section 4.0 ?electrical characteristics? . figure 2-5: device clock source figure 2-6: 16xclk and rx/rxir figure 2-7: 16xclk and tx/txir mcp2122 16xclk 16xclk rxir rx 16 16xclk 16 16xclk 3 clk 16 16xclk bit a bit b (input) (output) (input) 3 clk ( ~ 4 s) 16xclk tx txir 16 16xclk 16 16xclk 16 16xclk bit a bit b (input) (output) (input)
mcp2122 ds21894a-page 8 preliminary ? 2004 microchip technology inc. 2.4.1 baud rate the baud rate for the mcp2122 is determined by the frequency of the 16xclk signal. equation 2-1 demonstrates how to calculate the 16xclk frequency based on the desired baud rate. table 2-3 shows some common baud rates and the corresponding 16xclk frequency. equation 2-1: 16xclk frequency table 2-3: common baud rate/ 16xclk frequency 2.5 encoder/decoder the ir encoder/decoder is made up of two major components. they are: ? ir decoder ? ir encoder the encoder receives uart data (bit by bit) and outputs a data bit in the irda standard bit format. figure 2-8 shows a functional block diagram of the encoder. the decoder receives irda standard data (bit by bit) and outputs data in uart data bit format. figure 2-8 shows a functional block diagram of the decoder. the encoder/decoder has two interfaces. they are: ? host uart interface ?ir interface 2.5.1 encoding (modulation) each bit time is comprised of 16 bit clocks. if the value to be transmitted (as determined by the tx pin) is a logic-low, the txir pin will output a low level for 7-bit clock cycles, a logic-high level for 3-bit clock (with a maximum high-time of about 4 s) cycles, with the remaining time (6-bit clock cycles or more) being low. if the value to transmit is a logic-high, the txir pin will output a low level for th e entire 16 bit clock cycle. 2.5.2 decoding (demodulation) each bit time is comprised of 16 bit clocks. if the value to be received is a logic-low, the rxir pin will be a low level for the first 3-bit clock cycle (or a minimum of 1.6 s), with the remaining time (13-bit clock cycles) being high. if the value to be received is a logic high, the rxir pin will be a high level for the entire 16 bit clock cycle. the level on t he rx pin will be in the appropriate state for an entire 16-bit clock cycle. figure 2-8: mcp2122 receive detect to encoder/decoder block diagram baud rate 16xclk frequency (f 16 xclk ) comment 9600 153,600 19,200 307,200 38,400 614,400 57,600 921,600 115,200 1,843,200 f 16xclk 16 (desired baud rate) ? = txir glitch filter decode rx rxir pulse width limiter encode tx the following table shows the state on the reset pin and how this effects the operation of the txir pin. reset state comment v ih txir output encoded value of tx pin v il txir is forced low (~ 4 s)
? 2004 microchip technology inc. preliminary ds21894a-page 9 mcp2122 2.5.3 encoding and screen captures table 2-4 shows the txir pin high-time at different common baud rates. the internal txir pulse width high-time limiter is a featur e that minimizes the system current consumption at lower baud rates. the irda standard specification requires that optical receiver cir- cuitry detect pulses as narrow as 1.41 s (1.63 s is the typical time at 115200 baud). therefore, the time that the txir pin is high after this valid detection is additional current that is driv en by the emitter led. the mcp2122 will force the txir pin low after the pulse width limiter has timed out. figure 2-9 shows the mcp2122 16xclk, tx and txir waveforms at 115200 baud for a single tx low bit. in this case the txir is high for three 16xclk pulses. in figure 2-10 the mcp2122 is at 9600 baud for a single tx low bit. in this case the txir is high for 3.55 s. table 2-4: txir high pulse width figure 2-9: mcp2122 at 115200 baud waveform baud rate txir pulse width comment 3xt 16xclk pulse width limiter (2) 9600 19.53 s 4.00 s note 1 19200 9.77 s 4.00 s note 1 38400 4.88 s 4.00 s note 1 46875 4.00 s 4.00 s target crossover point 57600 3.26 s 4.00 s 115200 1.63 s 4.00 s note 1: the pulse width limiter on the txir pin saves system current for this baud rate. 2: this txir pulse width time is a design target and is not tested. actual times may be greater than or less than this value. 12345678910111213141516 jitter of the tx input relative to the 16xclk and txir 16xclk pulse ab txir
mcp2122 ds21894a-page 10 preliminary ? 2004 microchip technology inc. figure 2-10: mcp2122 at 9600 baud waveform 1 2 3 4 5 6 7 8 910 1112 13141516 16xclk pulse jitter of the tx input relative to the 16xclk and txir ab txir
? 2004 microchip technology inc. preliminary ds21894a-page 11 mcp2122 2.6 host uart interface the uart interface is used to communicate with the host controller. though a uart is capable of a full- duplex interface, the direct coupling to the ir encoder/ decoder allows only half-duplex operation (since the ir side is either receiving or transmitting and not both at the same time). this means that the system can not transmit and receive at the same time. 2.6.1 transmitting when the controller sends serial data to the mcp2122, the baud rates are required to match. there will be some jitter on the detection of the high to low edge of the start bit. this jitter will affect the place- ment of the encoded start bit. all subsequent bits will be 16 bitclk times later. while rxir is receiving data (low pulse), the txir pin is disabled from transmitting. 2.6.2 receiving when the controller receives serial data from the mcp2122, the baud rates are required to match. there will be some jitter on the detection of the high-to- low edge of the start bit. th is jitter will affect the placement of the decoded start bit. all subsequent bits will be 16 bitclk times later. the txir pin is disabled when data is being received (low pulse) on the rxir pin. 2.7 ir interface the ir interface is used to communicate with the optical receiver circuitry. the ir interface is either transmitting data or receiving data (half-duplex). 2.8 encoding/decoding jitter and offset figure 2-11 shows the jitter on the rxir and tx pins, and the offset on the rx pin and the txir pin. jitter is the possible variation of the desired edge. figure 2-9 and figure 2-10 show the jitter of the tx pin (range is indicated by red dashed lines). offset is the propagation delay of the input signal (rxir or tx) to the output signal (rx or txir). figure 2-9 and figure 2-10 show the offset of the txir pin from the 16xclk signal that starts the bit time. 2.9 minimizing power the device can be placed in a low power mode by forcing the reset pin low. this disables the internal state machine. to ensure that the lowest power con- sumption is obtained, ensure that the 16xclk pin is not active and that the other input pins (tx and rxir) are at a logic-high or logic-low level. 2.9.1 returning to operation when returning to normal operation, the reset pin must be forced high and the 16xclk signal should be operating. time should be given to ensure that the 16xclk is stabilized at the desired frequency before data is allowed to be transmitted or received. figure 2-11: effects of jitter and offset tx jitter 3 16xclk bitclk rxir rx tx txir 16 16xclk 16 16xclk 3 16xclk 16 16xclk rx jitter tx offset rx offset 16 16xclk
mcp2122 ds21894a-page 12 preliminary ? 2004 microchip technology inc. 3.0 development tools there are currently no de velopment tools for the mcp2122. a demo board is scheduled to be available soon.
? 2004 microchip technology inc. preliminary ds21894a-page 13 mcp2122 4.0 electrical characteristics absolute maximum ratings? ambient temperature under bias ................................................................................................. .......... ?40c to +125c storage temperature ............................................................................................................ .............. ... ?65c to +150c voltage on v dd with respect to v ss .......................................................................................................... ?0.3v to +6.5v voltage on reset with respect to v ss ..................................................................................................... ?0.3v to +14v voltage on all other pins with respect to v ss ................................................................................. ?0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ....800 mw max. current out of v ss pin ........................................................................................................................... .......500 ma max. current into v dd pin ........................................................................................................................... ..........500 ma input clamp current, i ik (vi < 0 or vi > v dd ) ................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ............................................................................................................. 20 ma max. output current sunk by any output pin.......... ........................................................................... .....................25 ma max. output current sourced by any output pin.................................................................................. ...................25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other condit ions above those indicated in the operation listings of this specificatio n is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp2122 ds21894a-page 14 preliminary ? 2004 microchip technology inc. figure 4-1: voltage-freque ncy (16xclk) graph, -40 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 4 frequency (mhz) v dd (volts) 2.0 1.8432 1.8
? 2004 microchip technology inc. preliminary ds21894a-page 15 mcp2122 4.1 dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) param. no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 1.8 ? 5.5 v see figure 4-1 d010 i dd supply current (2) ?0.1 1 maf osc = 1.8432 mhz, v dd = 5.5v (tx = h, rxir = h) transmitter (tx = l, rxir = h) ? ? 300 a f osc = 1.8432 mhz, v dd = 1.8v (4) ?? 1maf osc = 1.8432 mhz, v dd = 5.5v receiver (rxir = l, tx = h) ? ? 500 a f osc = 1.8432 mhz, v dd = 1.8v (4) ?? 2maf osc = 1.8432 mhz, v dd = 5.5v d020 i pd device disabled current (3) ? ? 2 a v dd = 1.8v (4) ?? 4 av dd = 5.5v note 1: data in the typical (?typ?) column is based on characterization results at +25 c. this data is for design guidance only and is not tested. 2: the supply current is mainly a fu nction of the operating voltage and fr equency. pin loading, pin rate and temperature have an impact on the current consumption. a)the test conditions for all i dd measurements are: 16xclk = external square wave, from rail-to-rail; tx = v ss , rxir = v ss , reset = v dd . 3: the device disable current is mainly a function of the operating voltage. tem perature also has an impact on the current consumption. when the device is disabled (reset = v ss ). the test conditions for all i dd measurements are: 16xclk = external square wave, from rail-to-rail; tx = v ss , rxir = v dd , reset = v ss ; the output pins are driving a high or low level into infinite impedance. 4: these parameters (shaded) are char acterized but are not te sted. these values should be used for design guidance only.
mcp2122 ds21894a-page 16 preliminary ? 2004 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) operating voltage v dd range as described in dc spec, section 4.1 ?dc characteristics? . param no. sym characteristic min typ (1) max units conditions v il input low voltage input pins d031 tx, rxir vss ? 0.2 v dd v d032 reset vss ? 0.2 v dd v d033 16xclk vss ? 0.2 v dd v v ih input high voltage input pins ? d041 tx, rxir 0.8 v dd ?v dd v d042 reset 0.8 v dd ?v dd v d043 16xclk 0.8 v dd ?v dd v i il input leakage current (2, 3) d060a tx, and 16xclk ? ? 1 a v ss v pin v dd , pin at high-impedance d061 reset ??1av ss v pin v dd d060b i ih rxir ? ? 1 a v dd = 5.5v, v rxir = v dd note 1: data in the typical (?typ?) column is ba sed on characterization results at +25 c. this data is for design guidance only and is not tested. 2: the leakage curr ent on the reset pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin.
? 2004 microchip technology inc. preliminary ds21894a-page 17 mcp2122 dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40c t a +125c (extended) operating voltage v dd range as described in dc spec, section 4.1 ?dc characteristics? . param no. sym characteristic min typ (1) max units conditions v ol output low voltage d080b rx ? ? 0.6 v i ol = 2 ma, v dd = 1.8v d081 txir ? ? 0.6 v i ol = 2 ma, v dd = 1.8v v oh output high voltage d090b rx (2) v dd ? 0.7 ? ? v i oh = -0.8 ma, v dd = 1.8v d091 txir (2) v dd ? 0.7 ? ? v i oh = -0.8 ma, v dd = 1.8v capacitive loading specs on output pins d101a c out all output pins ? ? 50 pf d101b c in all input pins ? 7 ? pf t a = +25 c, f c = 1.0 mhz note 1: data in the typical (?typ?) column is ba sed on characterization results at +25 c. this data is for design guidance only and is not tested. 2: negative current is defined as coming out of the pin.
mcp2122 ds21894a-page 18 preliminary ? 2004 microchip technology inc. 4.2 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 4.2.1 timing conditions the temperature and voltages specified in table 4-2 apply to all timing specifications unless otherwise noted. figure 4-2 specifies the load conditions for the timing specifications. table 4-1: symbology table 4-2: ac temperature and voltage specifications figure 4-2: load conditions for device timing specifications 1. tpps2pps 2. tpps t f frequency t time e error lowercase letters (pp) and their meanings: pp io input or output pin xclk oscillator rx receive tx transmit bitclk rx/tx bitclk rst reset uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z high-impedance ac characteristics standard operating conditions (unless otherwise stated) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range as described in dc spec, section 4.1 ?dc characteristics? . p in v ss c l c l = 50 pf for all output pins 7 pf (typical) for all input pins
? 2004 microchip technology inc. preliminary ds21894a-page 19 mcp2122 4.3 timing diagrams and specifications figure 4-3: external clock timing table 4-3: external clock timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ (1) max units conditions 1t xclk external 16xclk period (2, 3) 542.5 ? ? ns 1a f xclk external 16xclk frequency (2, 3) dc ? 1.8432 mhz 1c e xclk clock error (4, 5) ? ? 2 % note 5 3t xclk l, t xclk h clock in (16xclk) low or high time 50 ? ? ns 4t xclk r, t xclk f clock in (16xclk) rise or fall time (5) ? ? 7.5 ns note 5 note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization dat a for that particular oscillator type under standard operating conditions with the devi ce executing code. exceeding these specified limits may result in an unstable oscillator operation and/or hi gher than expected cu rrent consumption. when an external clock input is used, the ?max? cycl e time limit is ?dc? (no clock) for all devices. 3: a duty cycle of no more than 60/40 (high time/low time or low time/high time) is recommended for external clock inputs. 4: this is the clock error from the desired clock frequenc y. the total system clock error includes the error from the transmitter and the error of receiver (from the desired clock frequency). if the transmitter is 2% fast from the target frequency and the receiver is 2% slow from the target frequency, then the total error is 4%. 5: these parameters (shaded) are characterized but are not tested. these values should be used for design guidance only. 16xclk q4 q1 q2 q3 q4 q1 133 44
mcp2122 ds21894a-page 20 preliminary ? 2004 microchip technology inc. figure 4-4: i/o waveform table 4-4: i/o timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ (1) max units conditions 20a tor rx pin rise time (2, 3) ? 10 25 ns v dd 2.7v (note 3) 20b ? 10 60 ns v dd = 1.8v (note 3) 20c txir pin rise time (2, 3) ? 10 25 ns v dd 2.7v (note 3) 20d ? 10 60 ns v dd = 1.8v (note 3) 21a tof rx pin fall time (2, 3) ? 10 35 ns note 3 21c txir pin fall time (2, 3) ? 10 25 ns note 3 note 1: data in the typical (?typ?) column is at 5v, +25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: see figure 4-2 for loading conditions. 3: these parameters (shaded) are characterized but are not tested. these values should be used for design guidance only. 16xclk rx or 20, 21 old value new value note: refer to figure 4-2 for load conditions . txir pin
? 2004 microchip technology inc. preliminary ds21894a-page 21 mcp2122 figure 4-5: reset and device reset timer timing table 4-5: reset and device reset timer requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? . param. no. sym characteristic min typ (1) max units conditions 30 t rst l reset pulse width (low) 2000 ? ? ns v dd = 5.0 v 34a to d default output state of txir pin from reset low ? ? 2 s 34b to d default output state of rx pins from reset low ??2s note 1: data in the typical (?typ?) column is at 5v, +25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd reset internal reset 30 34a 34a txir pin rx pin 34b 34b
mcp2122 ds21894a-page 22 preliminary ? 2004 microchip technology inc. figure 4-6: tx and txir waveforms table 4-6: tx and txir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? . param. no. sym characteristic min typ (1) max units conditions ir100a t txbit transmit baud rate ? 16 ? t xclk ir100b t txirbit transmit baud rate 16 ? 16 t xclk ir102a e txbit host uart tx error ? ? 2 % note 2 , 3 ir102b e txirbit txir error from 16xclk ? 0 ? % note 2 , 4 ir113 t tx rf tx pin rise time and fall time ? ? 25 ns note 2 ir114 t txpdir j 16xclk to tx jitter ? ? 1 t xclk note 2 ir120 t tx l2 txir h tx falling edge ( ) to txir rising edge ( ) (1) 7?8t xclk ir121a t txir pw txir pulse width 3 ? 3 t xclk at 115200 baud ir121b 1.41 3.5 5 s at 9600 baud (note 5) ir122 t txir p txir bit period (1) ?16?t xclk ir123 t txir rf txir pin rise time and fall time ? ? 10 ns 50 pf load (note 2) note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. 2: these parameters (shaded) are characterized but are not tested. these values should be used for design guidance only. 3: the tx pin operation may be asynchronous to the 16xclk pin. this is the error from the desired baud rate for the system. 4: the txir pin operation is synchronous to the 16xclk pin. any error present on the 16xclk pin ( parameter 1c ) will be refelected on the txir pin. 5: this specification is not tested. th is value is from the design target. 16xclk tx txir 0100 0 1 ir100 ir121 bit bit bit bit bit ... ir122 ir122 ir122 ir122 ir122 ir122 ir114 ir113 ir113 ir115 ir120
? 2004 microchip technology inc. preliminary ds21894a-page 23 mcp2122 figure 4-7: 16xclk and the tx and txir waveforms table 4-7: tx and txir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? . param. no. symbol characteristic min typ (1) max units conditions ir113 t tx rf tx pin rise time and fall time ? ? 25 ns note 2 ir114 t tx j tx to 16xclk jitter ? ? 1 t xclk note 2 ir120 t tx l2 txir h tx falling edge ( ) to txir rising edge ( ) (1) 7? 8t xclk t txir pw txir pulse width smaller of smaller of ir121a 3 ? 3 t xclk at 115200 baud ir121b 1.41 3.5 5 s at 9600 baud (note 3) ir122 t txir p txir bit period ? 16 ? t xclk 20c t txir r txir pin rise time ? 10 25 ns v dd 2.7v (note 2) 20d ? 10 60 ns v dd = 1.8v (note 2) 21c t txir f txir pin fall time ? 10 25 ns note 2 note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. 2: these parameters (shaded) are characterized but are not tested. these values should be used for design guidance only. 3: this specification is not tested. th is value is from the design target 16xclk 01 data bit x data bit x+1 16 clk 16 clk bit value to tx ir121a 6 clk txiri (3 * 16xclk pulses) ir113 ir122 ir113 ir114 ir115 txir time out ir121c txir pin ir124 ir123 ir121b
mcp2122 ds21894a-page 24 preliminary ? 2004 microchip technology inc. figure 4-8: rxir and rx waveforms table 4-8: rxir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature: ?40 c t a +125 c (extended) operating voltage v dd range is described in section 4.1 ?dc characteristics? . param. no. sym characteristic min typ (1) max units conditions ir101a e rxirbit rxir error ? ? 2 % note 2 , 3 ir101b e rxbit host uart rx error ? 0 ? % note 2 , 4 ir103 t tx rf rx pin rise time and fall time ??25ns ir110 t rxbit receive (rx pin) bit rate 16 ? 16 t xclk ir130 t rxir l2 rx h rxir low and 16xclk edge ( or ) to rx falling edge ( ) ?4?t xclk at 115,200 baud ?3?t xclk at 9600 baud ir131a t rxir pw rxir pulse width 1.41 ? 3 t xclk s ir132 t rxir p rxir bit period (1) ?16?t xclk ir133 t rxir j 16xclk to rxir jitter ? ? 1 t xclk note 2 ir134 t rx skw 16xclk to rx skew ? ? 2.5 s ir135 t rxpdfil rxir filter 0.7 ? 1.4 s note 5 note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. 2: these parameters (shaded) are characterized but are no t tested. these values should be used for design guidance only. 3: the rxir pin operation is asynchronous to the 16xclk pin. this is the error from the desired baud rate for the system. 4: the rx pin operation is synchronous to the 16xclk pin. any error present on the 16xclk pin ( parameter 1c ) will be refelected on the rx pin. 5: the minimum specification ensures th at all pulses less then this pulse width are rejected, the maximum specification ensures that all pulses greater than th is pulse width are never rejected, and pulse widths between these may or may not be rejected. 16xclk rx rxir 0100 0 1 ir131a ir110 ir132 ir132 ir132 ir132 ir132 ir132 bit bit bit bit bit ... ir133 ir134 note: refer to figure 4-2 for load conditions. ir103 ir103 ir132 ir132 ir132 ir132 ir132 ir132 ir130
? 2004 microchip technology inc. preliminary ds21894a-page 25 mcp2122 5.0 dc and ac characterist ics graphs and tables the graphs and tables are not available at this time
mcp2122 ds21894a-page 26 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds21894a-page 27 mcp2122 6.0 packaging information 6.1 package marking information 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxxnnn yyww xxxxxxxx xxxyyww nnn gmcp2122 e/p256 0410 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer spec ific information. * standard device marking consists of microchip pa rt number, year code, week code, and traceability code.. gmcp2122 e/sn0410 256
mcp2122 ds21894a-page 28 preliminary ? 2004 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil body (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2004 microchip technology inc. preliminary ds21894a-page 29 mcp2122 8-lead plastic small outline (sn) ? narrow, 150 mil body (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
mcp2122 ds21894a-page 30 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds21894a-page 31 mcp2122 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support device mcp2122: infrared encoder/decoder temperature range e = -40 c to +125 c package p = plastic dip (300 mil, body), 8-lead sn = plastic soic (150 mil, body), 8-lead lead finish g = matte tin (pure sn) part no. x /xx package temperature range device examples: a) mcp2122-e/pg: extended temperature, pdip package, pb-free b) mcp2122-e/sng: extended temperature, soic package, pb-free c) mcp2122t-e/sng: tape and reel, extended temperature, soic package. pb-free x lead finish data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
mcp2122 ds21894a-page 32 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds21894a-page 33 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meet s with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzyl ab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:200 2 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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